PIC18F45K20-I/MV【PDF 230/234 页】MCU 32KB FLASH 1536B RAM 40-UQFN

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Sheet目录3873

226页 227页 228页 229页 [230页]231页 232页 233页 234页

2007 Microchip Technology Inc.

Preliminary

DS70165E-page 93

dsPIC33F

REGISTER 6-3:

INTCON1: INTERRUPT CONTROL REGISTER 1

R/W-0

NSTDIS

OVAERR

OVBERR

COVAERR

COVBERR

OVATE

OVBTE

COVTE

bit 15

bit 8

R/W-0

U-0

SFTACERR

DIV0ERR

DMACERR

MATHERR

ADDRERR

STKERR

OSCFAIL

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

NSTDIS: Interrupt Nesting Disable bit

= Interrupt nesting is disabled

= Interrupt nesting is enabled

bit 14

OVAERR: Accumulator A Overflow Trap Flag bit

= Trap was caused by overflow of Accumulator A

= Trap was not caused by overflow of Accumulator A

bit 13

OVBERR: Accumulator B Overflow Trap Flag bit

= Trap was caused by overflow of Accumulator B

= Trap was not caused by overflow of Accumulator B

bit 12

COVAERR: Accumulator A Catastrophic Overflow Trap Enable bit

= Trap was caused by catastrophic overflow of Accumulator A

= Trap was not caused by catastrophic overflow of Accumulator A

bit 11

COVBERR: Accumulator B Catastrophic Overflow Trap Enable bit

= Trap was caused by catastrophic overflow of Accumulator B

= Trap was not caused by catastrophic overflow of Accumulator B

bit 10

OVATE: Accumulator A Overflow Trap Enable bit

= Trap overflow of Accumulator A

= Trap disabled

bit 9

OVBTE: Accumulator B Overflow Trap Enable bit

= Trap overflow of Accumulator B

= Trap disabled

bit 8

COVTE: Catastrophic Overflow Trap Enable bit

= Trap on catastrophic overflow of Accumulator A or B enabled

= Trap disabled

bit 7

SFTACERR: Shift Accumulator Error Status bit

= Math error trap was caused by an invalid accumulator shift

= Math error trap was not caused by an invalid accumulator shift

bit 6

DIV0ERR: Arithmetic Error Status bit

= Math error trap was caused by a divide by zero

= Math error trap was not caused by a divide by zero

bit 5

DMACERR: DMA Controller Error Status bit

= DMA controller error trap has occurred

= DMA controller error trap has not occurred

bit 4

MATHERR: Arithmetic Error Status bit

= Math error trap has occurred

= Math error trap has not occurred

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